1999 imp, inc. 408-432-9100/www.impweb.com 1 applications computers and embedded controllers battery-operated systems intelligent instruments wireless communication systems pdas and handheld equipment block diagrams imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l p ower m anagement reset reset v cc 0.25ma reset generator 4.65v (IMP707) 4.40v (imp708) v cc + + mr IMP707 imp708 pfo gnd 1.25v + pfi 705_02.eps 1.25v + mr wdi imp705 imp706 imp813l wdo reset (reset) (imp813l) pfo gnd v cc 0.25ma reset generator 4.65v (imp705/813l) 4.40v (imp706) v cc + + pfi timebase watchdog timer transition detector 705_01.eps lo lo w w -p -p o o w w er er p super p super visor cir visor cir cuits cuits C w C w atc atc hdog timer hdog timer C br C br o o wnout det wnout det ection ection C p C p o o w w er suppl er suppl y monit y monit or or the imp705/706/707/708 and imp813l cmos supervisor circuits monitor power-supply and battery voltage level, and p/ c operation. compared to pin-compatible devices offered by maxim integrated products, imp devices feature 60 percent lower maximum supply current. the family offers several functional options. each device generates a reset signal during power-up, power-down and during brownout conditions. a reset is generated when the supply drops below 4.65v (imp705/707/813l) or 4.40v (imp706/708). for 3v power supply applications, refer to the imp705p/r/s/t data sheet. in addition, the imp705/706/813l feature a 1.6 second watchdog timer. the IMP707/708 have both active-high and active-low reset outputs but no watchdog function. the imp813l has the same pin-out and functions as the imp705 but has an active-high reset output. a versatile power-fail circuit has a 1.25v threshold, useful in checking battery levels and non-5v supplies. all devices have a manual reset (mr) input. the watchdog timer output will trigger a reset if connected to mr. all devices are available in 8-pin dip, so and microso packages. key features improved replacements for the maxim max705/6/7/8, max813l ?140? maximum supply current ?60% improvement precision power supply monitor ?4.65v threshold (imp705/707/813l) ?4.40v threshold (imp706/8) debounced manual reset input voltage monitor ?1.25v threshold ?battery monitor/auxiliary supply monitor watchdog timer (imp705/706/813l) 200ms reset pulse width active high reset output (IMP707/708/813l) microso package
2 408-432-9100/www.impweb.com ? 1999 imp, inc. imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l ordering information pin configuration IMP707 imp708 1 2 3 4 mr v cc gnd pfi reset reset nc pfo 8 7 6 5 IMP707 imp708 1 2 3 4 reset reset mr v cc nc pfo pfi gnd 8 7 6 5 1 2 3 4 mr v cc gnd pfi wdo reset (reset) wdi pfo 8 7 6 5 imp705 imp706 (imp813l) imp705 imp706 (imp813l) 1 2 3 4 reset (reset) wdo mr v cc wdi pfo pfi gnd 8 7 6 5 705_03.eps dip/so microso part number reset threshold (v) temperature range pins-package imp705 active low reset, watchdog output and manual reset imp705cpa 4.65 0 c to +70 c 8-plastic dip imp705csa 4.65 0 c to +70 c 8-so imp705cua 4.65 0 c to +70 c 8-microso imp705c/d 4.65 25 c dice imp705epa 4.65 40 c to +85 c 8-plastic dip imp705esa 4.65 40 c to +85 c 8-so imp706esa 4.40 40 c to +85 c 8-so imp706 active low reset, watchdog output and manual reset imp706cpa 4.40 0 c to +70 c 8-plastic dip imp706csa 4.40 0 c to +70 c 8-so imp706cua 4.40 0 c to +70 c 8-microso imp706c/d 4.40 25 c dice imp706epa 4.40 40 c to +85 c 8-plastic dip imp706esa 4.40 40 c to +85 c 8-so IMP707 active low & high reset with manual reset IMP707cpa 4.65 0 c to +70 c 8-plastic dip IMP707csa 4.65 0 c to +70 c 8-so IMP707cua 4.65 0 c to +70 c 8-microso IMP707c/d 4.65 25 c dice IMP707epa 4.65 40 c to +85 c 8-plastic dip IMP707esa 4.65 40 c to +85 c 8-so imp708 active low & high reset with manual reset imp708cpa 4.40 0 c to +70 c 8-plastic dip imp708csa 4.40 0 c to +70 c 8-so imp708cua 4.40 0 c to +70 c 8-microso imp708c/d 4.40 25 c dice imp708epa 4.40 40 c to +85 c 8-plastic dip imp708esa 4.40 40 c to +85 c 8-so imp813l active high reset, watchdog output and manual reset imp813lcpa 4.65 0 c to +70 c 8-plastic dip imp813lcsa 4.65 0 c to +70 c 8-so imp813lcua 4.65 0 c to +70 c 8-microso imp813lc/d 4.65 25 c dice imp813lepa 4.65 40 c to +85 c 8-plastic dip imp813lesa 4.65 40 c to +85 c 8-so
? 1999 imp, inc. 408-432-9100/www.impweb.com 3 imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l electrical characteristics absolute maximum ratings pin terminal voltage with respect to ground v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v to 6.0v all other inputs 1 . . . . . . . . . . . . . . . . . . . . . . . . 0.3v to (v cc + 0.3v) input current at v cc and gnd . . . . . . . . . . 20ma output current: all outputs . . . . . . . . . . . . . 20ma rate of rise at v cc . . . . . . . . . . . . . . . . . . . . . 100v/ s plastic dip power dissipation . . . . . . . . . . . 700 mw (derate 9 mw/ c above 70 c) so power dissipation . . . . . . . . . . . . . . . . . 470 mw (derate 5.9 mw/ c above 70 c) microso power dissipation . . . . . . . . . . . . . 330mw (derate 4.1 mw/ c above 70 c) operating temperature range imp705e/706e/707e/708e/813le . . . . . . . 40 c to 85 c imp706c/707c/708c/813lc . . . . . . . . . . . 0 c to 70 c storage temperature range . . . . . . . . . . . . . . 65 c to 160 c lead temperature soldering(10 sec) . . . . . . 300 c note: 1. the input voltage limits on pfi and mr can be exceeded if the input current is less than 10ma. these are stress ratings only and functional operation is not implied. parameter symbol conditions min typ max units operating voltage range v cc imp705/6/7/8c 1.2 5.5 v imp813l 1.1 5.5 imp705/6/7/8e, imp813le 1.2 5.5 supply current i cc imp705c/706c/813lc 75 140 a imp705e, imp706e, imp813le 75 140 IMP707c, imp708c 50 140 IMP707e, imp708e 50 140 reset threshold v rt imp705, IMP707, imp813l, note 2 4.50 4.65 4.75 v imp706, imp708, note 2 4.25 4.40 4.50 reset threshold hysteresis note 2 40 mv reset pulse width t rs note 2 140 200 280 ms mr pulse width t mr 0.15 s mr to reset out delay t md note 2 0.25 s mr input threshold v ih 2.0 v v il 0.8 mr pull-up current mr = 0v 100 250 600 a reset output voltage i source = 800 av cc - 1.5v v i sink = 3.2ma 0.4 imp705/6/7/8, v cc = 1.2v, i sink = 100 a 0.3 reset output voltage IMP707/708/813l, i source = 800 av cc - 1.5v v IMP707/708, i sink = 1.2ma 0.4 imp813l, i sink = 3.2ma 0.4 imp813l, v cc =1.2v, i source = 4 a 0.9 watchdog timeout period t wd imp705/706/813l 1.00 1.60 2.25 s wdi pulse width t wp v il = 0.4v, v ih = 0.8v cc 50 ns wdi input threshold v ih imp705/706/813l, v cc = 5v 3.5 v v il 0.8 wdi input current imp705/706/813l, wdi = v cc 50 150 a imp705/706/813l, wdi = 0v 150 50 wdo output voltage imp705/706/813l, i source = 800 av cc - 1.5v v imp705/706/813l, i sink = 1.2ma 0.4 pfi input threshold v cc = 5v 1.2 1.25 1.3 v pfi input current 25 0.01 25 na pfo output voltage i source = 800 av cc - 1.5v v i sink = 3.2ma 0.4 unless otherwise noted, v cc = 4.75v to 5.5v for the imp705/707/813l. v cc = 4.5v to 5.5v for the imp706/708 and over the operating temperature range. notes: 2. reset (imp705/6/7/8), reset (IMP707/8, imp813l)
4 408-432-9100/www.impweb.com ? 1999 imp, inc. imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l pin descriptions feature summary pin number imp705/706 IMP707/708 imp813l dip/so microso dip/so microso dip/so microso name function manual reset input. the active low input triggers a reset 1 3 1 3 1 3 mr pulse. a 250 a pull-up current allows the pin to be driven by ttl / cmos logic or shorted to ground with a switch. 2424 24v cc +5v power supply input. 3 5 3 5 3 5 gnd ground reference for all signals. power-fail voltage monitor input. with pfi less than 4 6 4 6 4 6 pfi 1.25v, pfo goes low. connect pfi to ground or v cc when not used. 5 7 5 7 5 7 pfo power-fail output. the output is active low and sinks current when pfi is less than 1.25v. watchdog input. wdi controls the internal watchdog timer. a high or low signal for 1.6sec at wdi allows the internal timer to run-out, setting wdo low. 68 6 8 wdi the watchdog function is disabled by floating wdi or by connecting wdi to a high-impedance three-state buffer. the internal watchdog timer clears when: reset is asserted; wdi is three-stated; or wdi sees a rising or falling edge. 6 nc not connected. active-low reset output. pulses low for 200ms when triggered, and stays low whenever v cc is below the reset threshold (imp705: 4.65v, imp705j: 4.00v, 7171 reset imp706: 4.40v). reset remains low for 200ms after v cc rises above the reset threshold or mr goes from low to high. a watchdog timeout will not trigger reset unless wdo is connected to mr. watchdog output. wdo pulls low when the 1.6 sec internal watchdog timer times-out and does not go high until the watchdog is cleared. in addition, when 82 8 2 wdo v cc is below the reset threshold, wdo remains low. unlike reset, wdo does not have a minimum pulse width and as soon as v cc exceeds the reset threshold, wdo goes high with no delay. 8 2 7 1 reset active-high reset output . reset is the inverse of reset. the imp813l has only a reset output. imp705 imp706 IMP707 imp708 imp813l power-fail detector brownout detection manual reset input power-up/down reset watchdog timer active-high reset output active-low reset output reset threshold 4.65v/4.00v 4.40v 4.65v 4.40v 4.65v
? 1999 imp, inc. 408-432-9100/www.impweb.com 5 imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l detail descriptions reset/reset operation the reset/reset signals are designed to start a p/ c in a known state or return the system to a known state. the IMP707/708 have two reset outputs, one active-high reset and one active-low reset output. the imp813l has only an active-high output. reset is simply the complement of reset. reset is guaranteed to be low with v cc above 1.2v. during a power-up sequence, reset remains low until the supply rises above the threshold level, either 4.65v, 4.40v or 4.00v.. reset goes high approximately 200ms after crossing the threshold. during power-down, reset goes low as v cc falls below the threshold level and is guaranteed to be under 0.4v with v cc above 1.2v. in a brownout situation where v cc falls below the threshold level, reset pulses low. if a brownout occurs during an already- initiated reset, the pulse will continue for a minimum of 140ms. auxiliary comparator all devices have an auxiliary comparator with 1.25v trip point and uncommitted output (pfo) and noninverting input (pfi). this comparator can be used as a supply voltage monitor with an external resistor voltage divider. the attenuated voltage at pfi should be set just below the 1.25 threshold. as the supply level falls, pfi is reduced causing the pfo output to transit low. normally pfo interrupts the processor so the system can be shut down in a controlled manner. 5v 0v 5v t wd t rs t wp t wd t wd 0v 5v 0v 5v 0v reset triggered by mr wdi wdo reset imp813l (reset) 705_05.eps figure 1. wdi three-state operation figure 2. watchdog timing 5v 0v 5v 0v 5v 0v 5v 0v v cc v rt wdo reset mr t md t rs t rs t mr mr extermally set low 705_04.eps manual reset (mr) the active-low manual reset input is pulled high by a 250 a pull-up current and can be driven low by cmos/ttl logic or a mechanical switch to ground. an external debounce circuit is unnecessary since the 140ms minimum reset time will debounce mechanical pushbutton switches. by connecting the watchdog output (wdo) and mr, a watchdog timeout forces reset to be generated. the imp813l should be used when an active-high reset is required. watchdog timer the watchdog timer available on the imp705/706/813l monitors p/ c activity. if activity is not detected within 1.6 seconds, the internal timer puts the watchdog output, wdo, into a low state. wdo will remain low until activity is detected at wdi. the watchdog function is disabled, meaning it is cleared and not counting, if wdi is floated or connected to a three-stated circuit. the watchdog timer is also disabled if reset is asserted. when reset becomes inactive and the wdi input sees a high or low transition as short as 50ns, the watchdog timer will begin a 1.6 second countdown. additional transitions at wdi will reset the watchdog timer and initiate a new countdown sequence. wdo will also become low and remain so, whenever the supply voltage, v cc , falls below the device threshold level. wdo goes high as soon as v cc transitions above the threshold. there is no minimum pulse width for wdo as there is for the reset outputs. if wdi is floated, wdo essentially acts as a low-power output indicator.
6 408-432-9100/www.impweb.com ? 1999 imp, inc. imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l application information imp70x v cc < 1.1v gnd reset 100k w 705_06.eps v cc ensuring that reset is valid down to v cc = 0v when v cc falls below 1.1v, the imp705-708 reset output no longer pulls down; it becomes indeterminate. to avoid the possi- bility that stray charges build up and force reset to the wrong state, a pull-down resistor should be connected to the reset pin, thus draining such charges to ground and holding reset low. the resistor value is not critical. a 100k ? resistor will pull reset to ground without loading it. bi-directional reset pin interfacing the imp705/6/7/8 can interface with p/ c bi-directional reset pins by connecting a 4.7k ? resistor in series with the reset output and the p/ c bi-directional reset pin. power supply imp70x v cc gnd gnd reset 4.7k ? 705_08.eps bi-directional i/o pin (example: 68hc11) buf buffered reset c or p reset input figure 3. ensuring that reset is valid down to v cc = 0v figure 3. bi-directional reset pin interfacing
? 1999 imp, inc. 408-432-9100/www.impweb.com 7 imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l monitoring voltages other than v cc the imp705-708 can monitor voltages other than v cc using the power fail circuitry. if a resistive divider is connected from the voltage to be monitored to the power fail input, pfi, the pfo (output) will go low if the divider voltage goes below its 1.25v reference. should hysteresis be desired, connect a resistor (equal to approximately 10 times the sum of the two resistors in the divider) between the pfi and pfo pins. a capacitor between pfi and gnd will reduce circuit sensitivity to input high-frequency noise. if it is desired to assert a reset in addition to the pfo flag, this may be achieved by connecting the pfo output to mr. monitoring a negative voltage the power-fail circuitry can also monitor a negative supply rail. when the negative rail is ok, pfo will be low, and when the negative rail is failing (not negative enough), pfo goes high (the opposite of when positive voltages are monitored). to trigger a reset, these outputs need to be inverted: adding the resistors and transistor as shown achieves this. the reset output will then have the same sense as for positive voltages: good = high, bad = low. it should be noted that this circuit? accuracy depends on the v cc line, the pfi threshold tolerance, and the resistors. imp70x v cc = 5v v in = 12v gnd v cc reset to processor 12v threshold ~10.87v pfo mr pfi 1m w 130k w 705_07.eps imp70x + +5v negative input voltage gnd v cc reset pfo mr pfi rp rn 705_09.eps 5 1 25 1 25 ? = ? .. rp v rn trip application information figure 4. monitoring voltages other than v cc figure 5. monitoring a negative voltage
imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l 8 408-432-9100/www.impweb.com ? 1999 imp, inc. e e1 d1 d ea eb c 0 15 a e b2 b a2 l a1 plastic dip (8-pin)a.eps plastic dip (8-pin)* 5 8 c h e e d b a1 a so (8-pin).eps inches millimeters min max min max plastic dip (8-pin) a 0.210 5.33 a1 0.015 0.38 a2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.36 0.56 b2 0.045 0.070 1.14 1.78 b3 0.030 0.045 0.80 1.14 d 0.355 0.400 9.02 10.16 d1 0.005 0.13 e 0.300 0.325 7.62 8.26 e1 0.240 0.280 6.10 7.11 e 0.100 2.54 ea 0.300 7.62 eb 0.430 10.92 ec 0.060 l 0.115 0.150 2.92 3.81 microso (8-pin) a 0.0433 1.10 a1 0.0020 0.0059 0.050 0.15 a2 0.0295 0.0374 0.75 0.95 b 0.0098 0.0157 0.25 0.40 c 0.0051 0.0091 0.13 0.23 d 0.1142 0.1220 2.90 3.10 e 0.0256 bsc 0.65 bsc e 0.193 bsc 4.90 bsc e1 0.1142 0.1220 2.90 3.10 l 0.0157 0.0276 0.40 0.70 a0 6 0 6 so (8-pin) a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.19 0.25 e 0.050 1.27 e 0.150 0.157 3.80 4.00 h 0.228 0.244 5.80 6.20 l 0.016 0.050 0.40 1.27 d 0.189 0.197 4.80 5.00 so (8-pin)*** microso (8-pin)** , v 57,5 5755h , 6 g/xkb7 * jedec drawing ms-001ba ** jedec drawing mo-187aa *** jedec drawing ms-012aa package dimensions
imp705/6/7/8, 8 imp705/6/7/8, 8 1 1 3l 3l imp, inc. corporate headquarters 2830 n. first street san jose, ca 95134-2071 tel: 408-432-9100 tel: 800-438-3722 fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com the imp logo is a registered trademark of imp, inc. all other company and product names are trademarks of their respective owners. ? 1999 imp, inc. printed in usa publication #: 1017 revision: a issue date: 08/17/99 type: preliminary
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